The present invention relates to a semiconductor device having a wiring structure in which an Al wiring layer is embedded in a interlayer-insulating film and manufacturing method thereof.
An Al wiring has been frequently used for a semiconductor device and an Al wiring made of an Al alloy mainly containing Al (hereafter, Al and Al alloy are generally referred to as Al) has been mainly used recently.
Particularly, an Al wiring (Al-RIE wiring) having a laminated structure is frequently used which is obtained by forming an Al film on a barrier metal film such as a TiN film for controlling the reaction with a lower-layer material or forming an antireflection film or an Al film for controlling the irregular reflection of light in a photolithography process and etching these laminated films through RIE.
However, this type of the Al-RIE wiring has a problem that an effective Al sectional area in a wiring sectional area is decreased due to the presence of the barrier metal film and antireflection film and thereby, the wiring resistance increases. Moreover, the Al-RIE wiring has a problem that the Al sectional area further decreases because RIE reaction products are deposited on the sidewall of the wiring under the RIE process of an Al film.
Furthermore, as the integration degree of an LSI is improved, it is necessary to form an Al wiring into a multilayer and the art for forming a plug for connecting upper and lower Al wirings becomes indispensable. There is a W(tungsten)-CVD art as one of the conventional plug forming arts, which shows a high step-coverage property.
FIG. 1 is a sectional view of a conventional multilayer Al wiring formed by the W-CVD art. In FIG. 1, a two-layer Al wiring is shown in which a first Al wiring 81 is connected to a second Al wiring 83 through a W plug 82. The first and second Al wirings 81 and 83 are formed respectively on a TiN/Ti barrier metal film 84 and moreover, upper sides of the first and second Al wirings 81 and 83 are respectively covered with a TiN antireflection fill m 85. Moreover, in FIG. 1, symbols 86 and 87 denote a fist interlayer-insulating film and a second interlayer-insulating film.
The W-CVD art includes two types such as "blanket deposition" and "selective deposition". The "blanket deposition" is a method of depositing a W film on the entire surface of a substrate including connection holes. The "selective deposition" is a method of selectively depositing a W film only on the bottom of a connection hole.
The both types can be realized in accordance with different heating conditions. However, though it is possible to fill the inside of a connection hole with a W film in one process in the case of the "selective deposition", etching-back process and CMP process for removing a W film from the outside of a connection hole are necessary as post-processes in the case of the "blanket deposition".
The W plug formed by the above-described W-CVD art has problems that it has a high resistance and lacks in the EM (electromigration) resistance.
The EM is a phenomenon in which Al atoms are moved due to collision of electrons when a current flows through an Al wiring. W is a material not easily causing the EM compared to Al. Therefore, by connecting upper and lower Al wirings each other by a W plug, the W plug serves as an EM diffusion barrier, Al accumulation occurs at the upstream side of an Al atom flow, and Al depletion occurs at the downstream side of the Al atom flow. This type of the Al accumulation or Al depletion causes hillock or void and resultantly causes a short circuit between wirings or disconnection of a wiring.
The above problem of the EM resistance is also present in an Al-RIE wiring. That is, this type of the Al wiring has problems that the Al&lt;111&gt; orientation degree is low, and the EM resistance cannot be secured because a barrier metal film such as a TiN film in which Al is not easily oriented is present as the substrate.
Moreover, the "entire-surface deposition" has a problem that the number of processes increases in addition to the above problem because a W film must be removed from the outside of a connection hole.
In the case of the "selective deposition", it is originally unnecessary to remove a W film from the outside of a connection hole. Actually, however, selectivity is frequently deteriorated and a W film is frequently formed on the outside of a connection hole. That is, the "selective deposition" also actually has a problem that it is necessary to remove a W film from the outside of a connection hole through etching-back later and thereby, the number of processes increases.
As other plug forming art, there is an Al reflow art for forming a plug by Al having a resistance lower than that of W. This art uses the flow characteristic based on the surface diffusion of an Al film, which makes it possible to fill the inside of a connection hole with an Al film by an easy method of heating a substrate and shorten a process by using the upper side of the Al film as a wiring. The Al reflow art has been variously studied so far, which frequently uses such substrate films as an Al film and a Ti (titanium) film having a high wettability.
Moreover, as the Al reflow art capable of lowering a flow temperature and expecting filling of a connection hole having a high A.R. (aspect ratio=connection-hole depth/connection-hole diameter), a two-step Al reflow art of sputter-forming an Al film without heating it and thereafter sputter-forming the Al film while heating it is known and is becoming a main stream.
Furthermore, many other Al reflow arts are proposed which are combined with a sputtering art having a high directivity such as the low-long throw sputtering method, collimation sputtering method, or HDP (High Density Plasma) sputtering method.
Because the Al reflow art forms an Al film by the sputtering method, the step coverage of the Al film is originally low. Therefore, the Al film at the bottom of a connection hole has a thin thickness. As a result, Al is agglomerated in a heating mode for fluidization and voids are produced inside of a connection hole. Therefore, the Al reflow art cannot fill a connection hole having a high aspect ratio.
To solve the above problem, agglomeration of Al is controlled by using a substrate film, such as a Ti film, having a high wettability with an Al film. However, when sputter-forming a Ti film, overhang of the Ti film occurs at the aperture of a connection hole and moreover, irregularity occurs on the surface of the Ti film. The irregularity is caused by the crystal plane dependency of Ti on crystal growth.
The above overhang and surface irregularity prevent an adhesion of Al and deteriorate the reflow characteristic. Moreover, even if using the directional sputtering method as a method for forming a Ti film, it is actually impossible to form a Ti film having a sufficient thickness on a connection hole.
Moreover, because Ti reacts on Al, an Al.sub.3 Ti film having a high resistance is formed on the bottom of a connection hole. Because the Al.sub.3 Ti film serves as an EM diffusion barrier the same as a W plug does, a problem occurs that the EM resistance is deteriorated.
Furthermore, it is recently studied to apply the Al reflow art to a wiring (DD wiring) having a damascene structure or a dual damascene structure. FIG. 2 shows a sectional view of a wiring having a conventional dual damascene structure formed by using the Al reflow art.
In FIG. 2, a first Al wiring 81 is embedded in a wiring groove 92 formed on the surface of a first layer-insulting film 86 and connected with a connection hole 88 formed on a second interlayer-insulating film 87 and a second Al wiring (hereafter referred to as DD wiring) 83 embedded in a wiring groove 89. In FIG. 2, symbol 90 denotes an Al.sub.3 Ti-alloy film and 91 denotes a third interlayer-insulating film.
The DD wiring 83 is obtained by previously forming the connection holes 88 the wiring groove and 89 in the second interlayer-insulating film 87, filling the insides of the connection holes 88 the wiring groove and 89 with an Al plug and an Al film serving as an Al wiring through one-time process at the same time, removing the outside extra Al film through CMP, and simultaneously forming the Al plug and the Al wiring. Therefore, it is possible to shorten the process and reduce the cost.
However, when using a Ti liner film as the substrate film of an Al film to form the DD wiring 83 by the Al reflow art, the following problems occur.
In the case of the above method, a connection hole and a wring groove are formed and thereafter, a Ti liner film (not shown) is formed on the entire surface to cover the entire inner surface (side and bottom) of the wiring groove with the Ti liner film.
Therefore, in the subsequent Al reflow process, an Al.sub.3 Ti film 90 is formed on the inner surface of the wiring groove and the effective Al volume of the DD wiring 83 decreases. Because the Al.sub.3 Ti film 90 has a high resistance, the resistance of the DD wiring 83 is increased. The increase of the wiring resistance becomes more serious problem as a wiring width is decreased.
Moreover, the Al.sub.3 Ti film 90 is formed on the bottom of the connection hole 88 to serve as an EM diffusion barrier. Therefore, a problem occurs that the EM resistance deteriorates similarly to the case of the W-CVD art.
As described above, various plug-forming arts have been proposed in which the Al reflow art is studied to form a DD wiring. However, because an Al film is agglomerated at the bottom of a connection hole, a problem occurs that it is impossible to fill a connection hole having a high aspect ratio.
To solve the above problem, it is proposed to use an Al film and a Ti liner film having a high wettability as an underlayer. However, a problem occurs that an Al.sub.3 Ti film is formed on the inner surface of a wiring groove and thereby, the wiring resistance increases and the EM resistance decreases.
As another prior art, when noticing only a local structure, a method is known that forms a metallic line in a patterned insulator layer in accordance with the CMP (Chemical Mechanical Polishing) planarization process by covering a patterned insulator layer for a via or the patterned insulator layer such as a wiring pattern with a Nb liner to form a Nb layer and attaching aluminum or an aluminum alloy onto the Nb layer. (Jap. Pat. Appln. KOKAI Publication No. 10-74764) According to this document, as a preferred embodiment, Nb.sub.2 O.sub.5 is formed by CMP the aluminum or aluminum alloy formed on a Nb layer, exposing a Nb liner with oxidized acidic colloidal alumina slurry, and oxidizing the Nb liner. As a result, the Nb layer serves as a polish-stopping layer. Therefore, this document does not have an intention for positively forming an AlNb alloy is prevented between the Nb liner and the aluminum or aluminum alloy. Also, there is an oxide film in an interface between Al and Nb. The AlNb alloy is prevented from being easily produced.